View IC61LV12816_280085.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IC61LV12816
Document Title
128K x 16 Hight Speed SRAM with 3.3V
Revision History
Revision No
0A 0B
1
Draft Date Remark
September 12,2001 April 23,2004
History
Initial Draft Revise typo on page 6
2 3 4 5 6 7 8 9 10 11 12
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution, Inc.
AHSR024-0B 04/23/2004
1
IC61LV12816
128K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
* * * * * High-speed access time: 8, 10, 12, and 15 ns CMOS low power operation TTL and CMOS compatible interface levels Single 3.3V 10%power supply Fully static operation: no clock or refresh required * Three state outputs * Data control for upper and lower bytes * Industrial temperature available
DESCRIPTION The ICSI IC61LV12816 is a high-speed, 2,097,152-bit static
RAM organized as 131,072 words by 16 bits. It is fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IC61LV12816 is packaged in the JEDEC standard 44-pin 400mil SOJ, 44-pin 400mil TSOP-2, and 48-pin 6*8mm TFBGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16 MEMORY ARRAY
VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT
COLUMN I/O
CE OE WE UB LB CONTROL CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution, Inc.
2
Integrated Circuit Solution, Inc.
AHSR024-0B 04/23/2004
IC61LV12816
PIN CONFIGURATIONS
44-Pin SOJ
A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
44-Pin TSOP-2
A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
1 2 3 4 5 6 7
48-Pin TF-BGA
1 A B C D E F G H
LB I/O0 I/O1 GND Vcc I/O6 I/O7 NC
8
2
OE UB I/O2 I/O3 I/O4 I/O5 NC A8
3
A0 A3 A5 NC NC A14 A12 A9
4
A1 A4 A6 A7 A16 A15 A13 A10
5
A2 CE I/O10 I/O11 I/O12 I/O13 WE A11
6
N/C I/O8 I/O9 Vcc GND I/O14 I/O15 NC
9 10 11 12
Integrated Circuit Solution, Inc.
AHSR024-0B 04/23/2004
3
IC61LV12816
PIN DESCRIPTIONS
A0-A16 I/O0-I/O15 CE OE WE LB UB NC Vcc GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C Vcc 3.3V 10% 3.3V 10%
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC VTERM TSTG TBIAS PT IOUT Parameter Power Supply Voltage Relative to GND Terminal Voltage with Respect to GND Storage Temperature Temperature Under Bias: Com. Ind. Power Dissipation DC Output Current (LOW) Value -0.5 to 4.0 -0.5 to Vcc+0.5 -65 to +150 -65 to +85 -45 to +90 2.0 +20 Unit V V C C C W mA
Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND VIN VCC GND VOUT VCC, Outputs Disabled Com. Ind. Com. Ind. Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 -- 2 -0.3 -1 -5 -1 -5 Max. -- 0.4 VCC + 0.3 0.8 1 5 1 5 Unit V V V V A A A A
Notes: 1. VIL (min.) = -2.0V for pulse width less than 10 ns. 2. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
4
Integrated Circuit Solution, Inc.
AHSR024-0B 04/23/2004
IC61LV12816
TRUTH TABLE
Mode Not Selected Output Disabled Read WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LB X X H L H L L H L UB X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Vcc Current ISB1, ISB2 ICC ICC
1 2 3 4
Write
ICC
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol ICC ISB1 Parameter Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., CE = VIL IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL CE VIH , f = 0 VCC = Max., CE VCC - 0.2V, VIN VCC - 0.2V, or VIN 0.2V, f = 0 Com. Ind. Com. Ind. Com. Ind. -8 ns Min. Max. -- -- -- -- -- -- 220 230 30 40 10 15 -10 ns Min. Max. -- -- -- -- -- -- 200 210 30 40 10 15 -12 ns Min. Max. -- -- -- -- -- -- 180 190 30 40 10 15 -15 ns Min. Max. -- -- -- -- -- -- 165 175 30 40 10 15 Unit mA mA
5 6 7 8 9 10 11 12
ISB2
mA
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Circuit Solution, Inc.
AHSR024-0B 04/23/2004
5
IC61LV12816
CAPACITANCE(1)
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Note: 1. Tested initially and after any design or process changes that may affect these parameters.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time
(2)
Min. 8 -- 3 -- -- -- 0 0 3 -- 0 0
Max. -- 8 -- 8 3 3 -- 3 -- 3 3 --
-10 Min. Max. 10 -- 3 -- -- -- 0 0 3 -- 0 0 -- 10 -- 10 4 4 -- 4 -- 4 4 --
-12 Min. Max. 12 -- 3 -- -- -- 0 0 3 -- 0 0 -- 12 -- 12 5 5 -- 5 -- 5 5 --
-15 Min. Max. 15 -- 3 -- -- 0 0 0 3 -- 0 0 -- 15 -- 15 6 6 -- 8 -- 6 6 --
Unit ns ns ns ns ns ns ns ns ns ns ns ns
tRC tAA tOHA tACE tDOE tHZOE tLZOE tLZCE tBA tHZB
(2) (2)
OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output
tHZCE(2)
(2)
tLZB(2)
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2
Notes: 1. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
AC TEST LOADS
319 3.3V
319 3.3V
OUTPUT 30 pF Including jig and scope 353
OUTPUT 5 pF Including jig and scope 353
Figure 1. 6
Figure 2. Integrated Circuit Solution, Inc.
AHSR024-0B 04/23/2004
IC61LV12816
AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
t RC
ADDRESS
1 2
t AA t OHA
DOUT
PREVIOUS DATA VALID
t OHA
DATA VALID
3 4
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA tOHA
5 6 7
tHZCE tHZB
DATA VALID
OE
tDOE tHZOE
CE
tLZCE
tLZOE tACE
LB, UB
tBA tLZB
8 9 10 11 12
DOUT
HIGH-Z
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition.
Integrated Circuit Solution, Inc.
AHSR024-0B 04/23/2004
7
IC61LV12816
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width Data Setup to Write End Data Hold from Write End Min. 8 7 7 0 0 7 7 4.5 0 -- 0 Max. -- -- -- -- -- -- -- -- -- 3 -- -10 Min. Max. 10 8 8 0 0 8 8 5 0 -- 0 -- -- -- -- -- -- -- -- -- 4 -- -12 Min. Max. 12 8 8 0 0 9 9 6 0 -- 0 -- -- -- -- -- -- -- -- -- 5 -- -15 Min. Max. 15 10 10 0 0 10 10 7 0 -- 0 -- -- -- -- -- -- -- -- -- 6 -- Unit ns ns ns ns ns ns ns ns ns ns ns
tWC tSCE tAW tHA tSA tPWB tPWE(4) tSD tHD
tHZWE(2) WE LOW to High-Z Output tLZWE(2) WE HIGH to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 4.Tested with OE Hith.
8
Integrated Circuit Solution, Inc.
AHSR024-0B 04/23/2004
IC61LV12816
AC WAVEFORMS WRITE CYCLE NO. 1
(1 ,2)(CE
Controlled, OE is HIGH or LOW)
t WC
ADDRESS
VALID ADDRESS
1
t HA
t SA
CE
t SCE
2 3 4
WE
t AW t PWE1 t PWE2 t PWB
UB, LB
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
5
t HD
DATAIN VALID
t SD
DIN
6 7 8 9 10 11 12
Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE).
Integrated Circuit Solution, Inc.
AHSR024-0B 04/23/2004
9
IC61LV12816
WRITE CYCLE NO. 2(1) (WE Controlled. OE is HIGH During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW t PWE1
WE
t SA
UB, LB
t PWB
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
OE CE
LOW
t HA
LOW
t AW t PWE2
WE
t SA
UB, LB
t PWB
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
10
Integrated Circuit Solution, Inc.
AHSR024-0B 04/23/2004
IC61LV12816
WRITE CYCLE NO. 4
(1,3)(LB,
UB Controlled, Back-to-Back Write)
t WC
ADDRESS
ADDRESS 1
t WC
ADDRESS 2
1 2
OE
t SA
CE
LOW
WE
t HA t SA t PWB t PWB
WORD 2
t HA
3 4
UB, LB
WORD 1
t HZWE
DOUT
HIGH-Z
t LZWE t HD
DATAIN VALID
DATA UNDEFINED
t SD
DIN
t SD
DATAIN VALID
t HD
5 6 7 8 9 10 11 12
Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
Integrated Circuit Solution, Inc.
AHSR024-0B 04/23/2004
11
IC61LV12816
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) 8 8 8 10 10 10 12 12 12 15 15 15 Order Part No. IC61LV12816-8B IC61LV12816-8K IC61LV12816-8T IC61LV12816-10B IC61LV12816-10K IC61LV12816-10T IC61LV12816-12B IC61LV12816-12K IC61LV12816-12T IC61LV12816-15B IC61LV12816-15K IC61LV12816-15T Package 6*8mm TF-BGA 400mil SOJ 400mil TSOP-2 6*8mm TF-BGA 400mil SOJ 400mil TSOP-2 6*8mm TF-BGA 400mil SOJ 400mil TSOP-2 6*8mm TF-BGA 400mil SOJ 400mil TSOP-2
ORDERING INFORMATION Industrial Range: -40C to +85C
Speed (ns) 8 8 8 10 10 10 12 12 12 15 15 15 Order Part No. IC61LV12816-8BI IC61LV12816-8KI IC61LV12816-8TI IC61LV12816-10BI IC61LV12816-10KI IC61LV12816-10TI IC61LV12816-12BI IC61LV12816-12KI IC61LV12816-12TI IC61LV12816-15BI IC61LV12816-15KI IC61LV12816-15TI Package 6*8mm TF-BGA 400mil SOJ 400mil TSOP-2 6*8mm TF-BGA 400mil SOJ 400mil TSOP-2 6*8mm TF-BGA 400mil SOJ 400mil TSOP-2 6*8mm TF-BGA 400mil SOJ 400mil TSOP-2
12
Integrated Circuit Solution, Inc.
AHSR024-0B 04/23/2004
IC61LV12816
1 2 3 4 5 6 7 8 9
Integrated Circuit Solution, Inc.
HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw
Integrated Circuit Solution, Inc.
AHSR024-0B 04/23/2004
10 11 12
13

▲Up To Search▲

Price & Availability of IC61LV12816

	To Download IC61LV12816 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .